The present invention relates to a shift redundancy circuit, a method for controlling a shift redundancy circuit, and a semiconductor memory device.
For semiconductor memory devices in recent years, demands for miniaturization, larger capacity, and lower power consumption are increasing. As semiconductor memory devices are miniaturized and designed to have larger capacity, deficiencies easily occur in their memories. This leads to a problem of productivity reduction, that is, yield reduction. Redundancy devices play an increasingly larger role in remedying such deficiencies and preventing yield reduction of semiconductor memory devices.
As a conventional redundancy device included in a semiconductor memory device, a shift redundancy circuit is disclosed, for example, in Japanese Laid-Open Patent Publication No. 2000-100191.
FIG. 1 is a block diagram describing an operation principle of a shift redundancy circuit 230. The shift redundancy circuit 230 includes a deficiency address hold circuit 231, a fuse signal generation circuit 232, a redundancy selection fuse circuit 233, a fuse signal amplification circuit 234, a fuse decoder circuit 235, a shift control circuit 236, an address decoder 237, and a selection driver 238.
In FIG. 1, a memory cell array AR is formed by, for example, four memory blocks BLK0 to BLK3. Each of the memory blocks BLK0 to BLK3 is selected based on block address signals ra0 and ra1. Four column selection lines cl0 to cl3 and one redundancy column selection line rcl, which commonly share each of the memory blocks BLK0 to BLK3, are arranged for the memory cell array AR. Further, four pre-column selection lines pcl0 to pcl3 are arranged for the four column selection lines cl0 to cl3.
The pre-column selection lines pcl0 to pcl3 are selected by the address decoder 237, based on column address signals ca0 and ca1. The pre-column selection lines pcl0 to pcl3 are connected, in a switchable manner, to the column selection lines cl0 to cl3 or to the redundancy column selection line rcl and the column selection lines cl0 to cl2, which are at bit positions adjacent to the bit positions of the column selection lines cl0 to cl3, by selection line switches RSW and SW0 to SW3 included in the selection driver 238.
In detail, shift signals sclj and scl0 to scl3 are respectively input into the selection line switches RSW and SW0 to SW3 from the shift control circuit 236, which will be described later. The pre-column selection lines pcl0 to pcl3 are connected, in a switchable manner, to the column selection lines cl0 to cl3, or to the redundancy column selection line rcl and the column selection lines cl0 to cl2, by the selection line switches SW0 to SW3 into which the corresponding shift signals scl0 to scl3 are input.
In the present example, when low (L) level shift signals scl0 to scl3 are respectively input into the selection line switches SW0 to SW3, the pre-column selection lines pcl0 to pcl3 are connected to the column selection lines cl0 to cl3. When high (H) level shift signals scl0 to scl3 are respectively input into the selection line switches SW0 to SW3, the pre-column selection lines pcl0 to pcl3 are connected to the redundancy column selection line rcl and the column selection lines cl0 to cl2.
When the pre-column selection line pcl0 is not connected to the redundancy column selection line rcl, the redundancy column selection line rcl is clamped to a low potential power supply Vss (e.g., to ground potential) by the selection line switch RSW into which an L level shift signal sclj is input.
The deficiency address hold circuit 231 includes a plurality of fuse circuits (not shown) for holding, when any of the memory blocks BLK0 to BLK3 includes a memory cell having a deficiency, an address selecting the memory cell as a deficiency address.
For example, as shown in FIG. 1, when the memory block BLK1 includes a memory cell having a first deficiency and the memory block BLK2 includes a memory cell having a second deficiency, the deficiency address hold circuit 231 holds a first deficiency address corresponding to the first deficiency and a second deficiency address corresponding to the second deficiency. To be specific, the deficiency address hold circuit 231 outputs address signals fa0 and fa1 indicating the first deficiency address, and address signals fb0 and fb1 indicating the second deficiency address.
The address signals fa0, fa1, fb0, and fb1, which are output from the deficiency address hold circuit 231, are complemented by the fuse signal generation circuit 232, and are generated as fuse signals fa0x, fa0z, fa1x, fa1z, fb0x, fb0z, fb1x, and fb1z, respectively.
When the memory blocks BLK1 and BLK2 are selected, the redundancy selection fuse circuit 233 outputs redundancy selection signals faj and fbj for respectively remedying the first deficiency and the second deficiency, in response to memory block selection signals ba0 and ba1 from a memory block selection circuit, which is not shown.
The redundancy selection signals faj and fbj, which are output from the redundancy selection fuse circuit 233, are amplified by the fuse signal amplification circuit 234, and are generated as fuse signals cfaj and cfbj, respectively.
The fuse decoder circuit 235 decodes the fuse signals fa0x, fa0z, fa1x, fa1z, fb0x, fb0z, fb1x, and fb1z, which are output from the fuse signal generation circuit 232, and the fuse signals cfaj and cfbj, which are output from the fuse signal amplification circuit 234, to generate decode signals cfj and cf0 to cf3, respectively.
The shift control circuit 236 generates shift signals sclj and scl0 to csl3 for controlling the switching of the selection line switches RSW and SW0 to SW3 based on the decode signals cfj and cf0 to cf3, which are output from the fuse decoder circuit 235.
The following describes the operation of the shift redundancy circuit 230 with the above-described structure.
When the memory block BLK0 is selected, the memory block selection signals ba0 and ba1 are both set at an L level because the memory block BLK0 has no deficiency, and the redundancy selection signals faj and fbj are both set at an L level.
In this state, the shift control circuit 236 generates L level shift signals sclj and scl0 to scl3 in response to the decode signals cfj and cf0 to cf3 output from the fuse decoder circuit 235.
Thus, the pre-column selection lines pcl0 to pcl3 are connected to the column selection lines cl0 to cl3 by the selection line switches SW0 to SW3, respectively. The redundancy column selection line rcl is clamped to ground potential by the selection line switch RSW.
When the memory block BLK1 is selected, the memory block selection signal ba0 is set at an H level and the memory block selection signal ba1 is set at an L level because the memory block BLK1 has a first deficiency. Thus, the redundancy selection signal faj is set at an H level and the redundancy selection signal fbj is set at an L level.
In this state, the shift control circuit 236 generates H level shift signals sclj and scl0 to scl2 and an L level shift signal scl3 in response to the decode signals cfj and cf0 to cf3 output from the fuse decoder circuit 235.
Thus, the pre-column selection lines pcl0 to pcl2 are connected to the redundancy column selection line rcl and the column selection lines cl0 and cl1 by the selection line switches. SW0 to SW2, respectively. The pre-column selection line pcl3 is connected to the column selection line cl3 by the selection line switch SW3. The column selection line cl2 is not selected (connected to neither the pre-column selection line pcl2 nor pcl3).
When the memory block BLK2 is selected, the memory block selection signal ba0 is set at an L level and the memory block selection signal ba1 is set at an H level because the memory block BLK2 has a second deficiency. Thus, the redundancy selection signal faj is set at an L level and the redundancy selection signal fbj is set at an H level.
In this state, the shift control circuit 236 generates H level shift signals sclj, scl0, and scl1, and L level shift signals scl2 and scl3 in response to the decode signals cfj and cf0 to cf3 output from the fuse decoder circuit 235.
Thus, the pre-column selection lines pcl0 and pcl1 are connected to the redundancy column selection line rcl and the column selection line cl0 by the selection line switches SW0 and SW1, respectively. The pre-column selection lines pcl2 and pcl3 are connected to the column selection lines cl2 and cl3 by the selection line switches SW2 and SW3, respectively. The column selection line cl1 is not selected (connected to neither the pre-column selection line pcl1 nor pcl2).
When the memory block BLK3 is selected, the shift control circuit 236 generates L level shift signals sclj and scl0 to scl3 in the same manner as when the memory block BLK0 described above is selected because the memory block BLK3 has no deficiency. Thus, the pre-column selection lines pcl0 to pcl3 are connected to the column selection lines cl0 to cl3 by the selection line switches SW0 to SW3, respectively. The redundancy selection line rcl is clamped to ground potential by the selection line switch RSW.
In this way, in the shift redundancy circuit 230, the shift control circuit 236 operates according to the redundancy selection signals faj and fbj, which are generated based on the memory block selection signals ba0 and ba1. Then, the switching of the selection line switches RSW and SW0 to SW3 is controlled according to the shift signals sclj and scl0 to scl3, which are generated by the shift control circuit 236.
As a result, when the memory block BLK1 is selected, connection destinations of the pre-column selection lines pcl0 to pcl2 are switched to be sequentially shifted from the column selection lines cl0 to cl2 to the redundancy column selection line rcl and the column selection lines cl0 and cl1, which are at bit positions adjacent to the bit positions of the column selection lines cl0 to cl2. This switching realizes the memory block BLK1 with no deficiency.
Also, when the memory block BLK2 is selected, connection destinations of the pre-column selection lines pcl0 and pcl1 are switched to be sequentially shifted from the column selection lines cl0 and cl1 to the redundancy column selection line rcl and the column selection line cl0, which are at bit positions adjacent to the bit positions of the column selection lines cl0 and cl1. This switching realizes the memory block BLK2 with no deficiency.
With the conventional structure described above, the shift control circuit 236 operates to change the states of the shift signals sclj and scl0 to scl3 every time when the memory blocks BLK0 to BLK3 that are selected are switched. Then, the selection line switches RSW and SW0 to SW3 are switched based on those shift signals. This slows the switching of the selection line switches RSW and SW0 to SW3. As a result, the switching of the memory blocks BLK0 to BLK3 fails to be executed at a high speed.
Further, the shift control circuit 236 operates every time when the memory blocks BLK0 to BLK3 are switched. This increases the operation current of the shift control circuit 236, and thereby increases power consumption.
Accordingly, it is an object of the present invention to provide a shift redundancy circuit, a method for controlling the shift redundancy circuit, and a semiconductor memory device that enable a switching operation of memory blocks to be executed at a high speed and reduce current consumption relating to the switching operation.